Dear Mike,
Thanks for your productive information.
May I think your information results that the combined footprint
would be smaller than the sum of the SBP-2 initiator and SBP-2
target footprints?
Also I think SBP-2 is really well designed to support memory-
bus architecture provided by IEEE 1394. So if we adopt socket
stream API on SBP-2, I am afraid of that we might bring some
drawbacks from conventional I/O channel like architecture.
--------------------------------------------
-------------------------------
Fumio Nagasaka
Epson Software Development Laboratory Inc.
Tel +81 268 25 4111, Fax +81 268 25 4627
E-mail to nagasaka.fumio at exc.epson.co.jp
-----Original Message-----
From: Michael D. Johas Teener - CTO & CoB, Zayante, Inc [SMTP:mike at zayante.com]
Sent: Saturday, February 14, 1998 2:08 AM
To: Nagasaka Fumio
Cc: Stephen Holmstead; 'Turner, Randy'; 'Brian Batchelder'; p1394 at pwg.org; pp1394 ML
Subject: RE: P1394> Rough SBP-2 & IP1394 core component ROM sizes
Regarding the note from Nagasaka Fumio:
>I agree with Stephen,
>> Also, I don’t believe any of the chip manufacturers support SBP-2
>>for
>both target and initiator.
>>Do we need to develop a firmware which supports two LINK ICs
>one for initiator and one for target?
>I think “yes”. Because typical LINK IC has only one input
>FIFO in
>each chip. And it is very difficult to implement two different software
>stack utilizing one i/o channel.
1) All of the Pele-based designs (OpenHCI, among others) do an excellent
job as both initiator and target ... indeed, they can support an almost
unlimited number of simultaneous initiator and target contexts
simultaneously. They are, however, PCI bus master designs ... so unless you
are building a relatively high-end printer, they may not be in your price
range (but check with IC suppliers like Sony, Symbios, and FFM for Pele,
and virtually everyone about OpenHCI).
2) Sony has a fine SBP-2 target part that is also useful for initiator use,
but requires more software and external DMA interaction.
3) The number of input FIFOs is not too important, except as an
optimization, particularly when inbound bus bridging is provided (useful
for CPU-type initiators). The key is to have good receive DMA into the
controller memory.
4) 1394 is quite different from traditional "I/O channels" ... mainly
because it's really a memory bus. If you treat it correctly (as a memory
bus), then it is quite simple to implement multiple stacks using the same
hardware. Indeed, our own proto systems implement as many as 4 protocol
stacks using relatively primative hardware.
===========================================================================
Michael D. Johas Teener, Chief Technical Officer & Chairman of the Board
Zayante, Inc., 269 Mt. Hermon Rd. #111, Scotts Valley, CA 95066-4000, USA
email: mike at zayante.com voice: +1-408-461-4901 fax: +1-408-461-1394
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