"McDonald, Ira" wrote:
> ...
> Also, what about 'mips5' since the R5 generation has been
> shipping for several years?
I'm pretty sure that there are only 4 instruction set revs
through the R12000. MIPS-1 was the instruction set provided
on all the MIPS chips up through the R3000; the R4000 series
added the MIPS-2 and MIPS-3 instruction sets (MIPS-2 adds
some new 32-bit instructions, MIPS-3 is the 64-bit version);
the R5000 and newer add the MIPS-4 instruction set (new
multiple-add instruction, plus other junk...)
> Also, 'sparc-32' and 'sparc-64', since UltraSPARC native code
> is NOT compatible with SPARC.
Right.
> I've been saying for several months that the IPP WG members
> are NOT qualified to populate an IANA registry of "cpu-type"
> keywords - I STRONGLY urge that this field be changed to
> descriptive text (human-consumable but NOT machine-consumable).
It could be something as simple as the manufacturer's chip
number (e.g. MC68000 for a Motorola 68000 CPU); there is some
use in grouping some processors, but I agree that the current
keywords don't cover things right.
> Lastly, what the heck is 'itantium' supposed to be? Is this
> an Intel/HP IA-64 family CPU?
Using the naming in the spec, it would probably be "x86-64", but
that ignores differences between processors, e.g. MMX vs. non-MMX,
instruction sets, etc.
As I recall, McKinley will have some new instructions, even though
it too will be 64-bit...
-- ______________________________________________________________________ Michael Sweet, Easy Software Products mike@easysw.com Printing Software for UNIX http://www.easysw.com
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