IPP Mail Archive: RE: IPP> DRV - Client Print Support Files

RE: IPP> DRV - Client Print Support Files Internet-Draft down-loa ded

From: McDonald, Ira (imcdonald@sharplabs.com)
Date: Thu Nov 09 2000 - 12:57:29 EST

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    Hi Carl-Uno,

    Actually Tom did NOT get the values from the IANA registry.
    It doesn't distinguish between 16- and 32-bit Intel 80x86
    processors at all.

    Also, the IANA registry was last updated FOUR YEARS ago.
    It's a dead file we'd need to revive if we wanted to use
    it for the IPP driver download feature.

    Cheers,
    - Ira McDonald

    -----Original Message-----
    From: Carl-Uno Manros [mailto:carl@manros.com]
    Sent: Wednesday, November 08, 2000 7:43 PM
    To: Michael Sweet; McDonald, Ira
    Cc: Hastings, Tom N; ipp (E-mail)
    Subject: RE: IPP> DRV - Client Print Support Files Internet-Draft
    down-loaded

    All,

    This is all an interesting discussion, but I know that Tom got his set of
    values from the actual IANA registry for processor names. I was also rather
    puzzled by some of the names, but these are the ones actually registered,
    like it or not.

    Do you want to volonteer to go out and kick Intel, Motorola and others to do
    a better job of registering their processors?

    Carl-Uno

    > -----Original Message-----
    > From: owner-ipp@pwg.org [mailto:owner-ipp@pwg.org]On Behalf Of Michael
    > Sweet
    > Sent: Wednesday, November 08, 2000 11:08 AM
    > To: McDonald, Ira
    > Cc: Hastings, Tom N; ipp (E-mail)
    > Subject: Re: IPP> DRV - Client Print Support Files Internet-Draft
    > down-loaded
    >
    >
    > "McDonald, Ira" wrote:
    > > ...
    > > Also, what about 'mips5' since the R5 generation has been
    > > shipping for several years?
    >
    > I'm pretty sure that there are only 4 instruction set revs
    > through the R12000. MIPS-1 was the instruction set provided
    > on all the MIPS chips up through the R3000; the R4000 series
    > added the MIPS-2 and MIPS-3 instruction sets (MIPS-2 adds
    > some new 32-bit instructions, MIPS-3 is the 64-bit version);
    > the R5000 and newer add the MIPS-4 instruction set (new
    > multiple-add instruction, plus other junk...)
    >
    > > Also, 'sparc-32' and 'sparc-64', since UltraSPARC native code
    > > is NOT compatible with SPARC.
    >
    > Right.
    >
    > > I've been saying for several months that the IPP WG members
    > > are NOT qualified to populate an IANA registry of "cpu-type"
    > > keywords - I STRONGLY urge that this field be changed to
    > > descriptive text (human-consumable but NOT machine-consumable).
    >
    > It could be something as simple as the manufacturer's chip
    > number (e.g. MC68000 for a Motorola 68000 CPU); there is some
    > use in grouping some processors, but I agree that the current
    > keywords don't cover things right.
    >
    > > Lastly, what the heck is 'itantium' supposed to be? Is this
    > > an Intel/HP IA-64 family CPU?
    >
    > Using the naming in the spec, it would probably be "x86-64", but
    > that ignores differences between processors, e.g. MMX vs. non-MMX,
    > instruction sets, etc.
    >
    > As I recall, McKinley will have some new instructions, even though
    > it too will be 64-bit...
    >
    > --
    > ______________________________________________________________________
    > Michael Sweet, Easy Software Products mike@easysw.com
    > Printing Software for UNIX http://www.easysw.com
    >



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